1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, by which process integration of a transistor capable of a multi-bit operation on a cell array area and a metal oxide semiconductor field effect transistor (MOSFET) on a peripheral circuit area is facilitated simultaneously.
2. Description of the Related Art
Silicon-oxide-nitride-oxide-silicon (SONOS) or metal-oxide-nitride-oxide-silicon (MONOS) devices have been proposed as non-volatile memory devices that are widely used in mobile communications systems, memory cards, etc. Most of such SONOS semiconductor memory devices employ a stacked SONOS transistor structure in which an ONO structure exists over the entire channel area of a transistor. In this stacked SONOS transistor structure, since an ONO structure exists over the entire channel area of a transistor, the cell transistor has a high initial threshold voltage Vth and a high program current. Hence, integrating the stacked SONOS transistor together with a logic product having a low initial threshold voltage Vth into a single chip is difficult due to the high initial threshold voltage Vth. Also, in a stacked SONOS-type cell transistor, electrons trapped in a storage node layer within an ONO structure may move horizontally along the storage node layer, and thus an erasing operation may not be properly performed. Furthermore, as an FET is scaled to a high level with rapid development of the semiconductor industry, various problems, such as an increase in leakage current due to a reduction of the size of a semiconductor device, occur.
To operate a general flash memory device, there is a need to form a cell transistor array on a cell array area and also form a low voltage (LV) or high voltage (HV) MOSFET circuit block, including such circuits as a program/erase (P/E) controller, a data load latch, a word line decoder, an address buffer, and a sense amp, on a peripheral circuit area and a core area (hereinafter, both referred to as a peripheral circuit area). To integrate a cell transistor array having a storage node and circuit blocks of a peripheral circuit area into a single chip as in a SONOS structure, efficient process integration between a cell array area and the peripheral circuit is required. In particular, when a cell transistor having a structure capable of a multi-bit operation using localized bits is formed, a process of forming a cell transistor array on a cell array area and a process of forming an HV transistor and a LV transistor on a peripheral circuit area are simultaneously performed. In this case, a process of readily forming transistors having structures designed differently according to unique functions of the transistors to maintain the unique functions and electrical characteristics of the transistors is needed.